1. Technical Field
The present disclosure relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a redundancy memory block and a cell array structure thereof, which is advantageous from the standpoint of flexibility and is capable of lessening a design overhead and permitting an efficient repair.
2. Discussion of Related Art
In general, the fabrication of a semiconductor memory device is completed in a wafer state, and respective memory chips on the wafer undergo various tests. A test to check whether circuit devices of respective memory chips operate according to a predetermined specification is necessarily performed. In the test, various electrical characteristics and operations for the chips are tested through diverse test parameters. When any one of the control circuits within a semiconductor memory chip is defective based on the test result, a repair of the defective semiconductor memory device is actually impossible, but when a memory cell within a memory cell array is defective, the defective memory cell can be replaced with a redundancy memory cell through the repair process, that is, the repair of a detected defect is valid. In other words, when a portion of normal memory cells is decided as being defective, the repair may be performed by using a redundancy memory cell provided as an extra, thus permitting normal operation of the semiconductor memory device.
Redundancy memory cells provided as extra memory cells are required to repair defective memory cells in a large capacity semiconductor memory device. In this case, when a normal memory cell has a defect and the repair therefore is performed by using a redundancy memory cell, a speed slow-down problem may occur, and this may seriously influence the performance and operation of the device. Various schemes to solve such a problem have been proposed.
FIG. 1 illustrates a memory cell array structure according to conventional art.
As shown in FIG. 1, a general semiconductor memory device, particularly a memory cell array of SRAM, comprises a plurality of mats, including a plurality of sub-mats 10. As used herein, a memory mat may be thought of as a memory bank and a sub-mat as a memory sub-bank. The sub-mat 10 comprises a plurality of normal memory blocks MB, a plurality of normal sub-row decoders SRD, and one normal main row decoder MRD. The plurality of normal memory blocks MB are arrayed in a line, and a normal sub-row decoder SRD is disposed between mutually adjacent normal memory blocks MB. The normal main row decoder MRD is disposed near an edge of a normal memory block MB located at the end of the line.
The semiconductor memory device is provided with a structure in which one normal main word line MWL is selected by the normal main row decoder MRD and at least one sub-word line SWL is enabled by the normal sub-row decoder SRD responding to a signal that is provided through the normal main word line MWL. Though not shown in the drawings, related-circuits including a normal column decoder for enabling a column or bit line are disposed in each normal memory block.
FIG. 2 illustrates a layout example of redundancy cells for the repair of a normal memory cell having a defect in a semiconductor memory device with the structure described above according to a conventional art.
As shown in FIG. 2, a memory cell array structure 20 in a conventional semiconductor memory device further comprises redundancy cell areas RCA and RRA for a repair. The redundancy cell areas RCA and RRA are provided as an additional configuration, that is, a redundancy column area RCA for a column line repair and a redundancy row area RRA for a row line repair are provided.
The redundancy column area RCA is disposed near an edge of a normal memory block MB of a line of mutually adjacent normal memory cell blocks MB, and is disposed so that a redundancy column line has the same length as a column line of normal memory block MB. The redundancy row area RRA is disposed so that a redundancy row line is longer than or equal to a length of a normal main word line MWL shown in FIG. 1. Further, the redundancy row area RRA is formed being disposed in a lower part of an area to connect between all of the plurality of normal memory blocks MB disposed adjacent one another in a given direction.
The repair using the redundancy column area RCA is performed by a specific redundancy column decoder (not shown). The redundancy row area RRA also requires a specific redundancy sub-row decoder (not shown) to repair a row line corresponding to an MWL.
In the conventional cell array structure described above, the redundancy column area RCA and the redundancy row area RRA are separated from each other. Therefore, when a number of repairs for the column lines or row lines are required, the redundancy efficiency falls. That is, it is disadvantageous from the standpoint of flexibility. Furthermore, the redundancy row area RRA has a structural difference from a normal memory block MB, thus causing increased design overhead.